Chip scale packages (CSP) are widely adopted for semiconductor chip assemblies in the industry since the component has a smaller size. Wafer-level chip-scale packages (WLCSP) are considered a popular type of CSP. The use of wafer-level chip-scale packages employs a method in which the pads may be etched or printed directly onto the silicon wafer, resulting in the package being very close to the size of the silicon dies. A semiconductor device made with a WLCSP usually has a smaller size and no bonding wires at all.
When using wafer-level chip-scale packages, a common issue involves a mismatch in the coefficient of thermal expansion (CTE) between multi-layers, dissimilar materials (e.g., between redistribution layer (RDL), solder ball, printed circuit board (PCB)), and associated insulating layers. The CTE mismatch creates high stress during a reliability test, which leads to premature fatigue or cracking in the solder ball. Thus, a package structure or a method for reducing the mismatch in the CTE is still in great demand.